Electronic devices such as field-effect transistors have hitherto been produced through element production processes conducted under high vacuum, such as vapor deposition, PVD (physical vapor deposition), and CVD (chemical vapor deposition). The production lines hence have necessitated expensive equipment and required much energy.
Meanwhile, semiconductor materials for coating process, from which semiconductor layers can be formed by a coating process, have an advantage that an electronic device having a large area can be produced at low cost with low energy without requiring expensive equipment.
An example of such semiconductor materials is shown in patent document 1, which includes a statement to the effect that a bicyclic compound is applied to a substrate and converted to a semiconductor material to produce a field-effect transistor. In this process, a bicyclic compound having high solubility is heated to thereby eliminate ethylene therefrom and convert the structure thereof into a highly planar structure. Thus, an organic semiconductor layer having high crystallinity is formed from an organic thin film which is amorphous or substantially amorphous. Consequently, the bicyclic compound, even though bicyclic compound with low molecular weight, can form a film through a coating process and a field-effect transistor having a higher mobility can be formed.
Meanwhile, a technique is known in which the contact resistance which arises at an electrode/interface of a bottom contact type field-effect transistor is reduced by controlling the shape of the electrode. Patent document 2 includes a statement to the effect that in the case of a source/drain electrode having a tapered portion on the channel side, a reduction in contact resistance can be attained by regulating the channel-length-direction width of the tapered portion so as to be less than the average grain diameter of the semiconductor crystals. Specifically, a Cr adhesion layer and a source/drain electrode constituted of Au are formed so that a cross-section thereof forms an angle (taper angle) of 45° or larger with the substrate, and the tapered portion is regulated so as to have a width that is smaller than 50 nm, which is the average size of the pentacene crystals to be generated on the electrode by vacuum deposition. Thus, a reduction in contact resistance is attained. This technique is a contrivance by which the semiconductor crystals to be in contact with the region located within a height of 10 nm from the gate insulator that forms a channel are prevented from growing from nuclei present on the electrode. The patent document hence includes a statement to the effect that even when the source/drain electrode is formed in a normally tapered shape or an inversely tapered shape with respect to the substrate, a reduction in contact resistance is possible equally.
Furthermore, patent document 3 and patent document 4 describe transistors which each include a source/drain electrode having a tapered shape, as improvements of the prior-art technique disclosed in patent document 2. Patent document 3 discloses a technique in which an organic-compound layer is disposed selectively at the interface between a source electrode and a semiconductor layer or at the interface between a drain electrode and a semiconductor layer to thereby reduce image force during carrier movement, facilitate tunneling, and obtain a large operating frequency and small power consumption. Patent document 4 discloses a technique in which a planarization layer is disposed over the groove present between a source electrode and a drain electrode to thereby improve the mobility of charges regardless of the shapes of the source electrode and drain electrode. These patent documents each disclose a technical idea which does riot relate to a tapered electrode shape.